1. Field of the Invention
This invention relates to integrated circuit devices, and more particularly to a method and apparatus for digitally controlling the capacitance of integrated circuit components using MOS field effect transistors.
2. Description of Related Art
One well-known problem to those skilled in the art of the design and manufacture of integrated circuits is the poor tolerance values associated with integrated circuit components, especially the tolerance values of passive circuit components. Due to process variations, device parameter spread, variations in critical parameters such as conductive layer sheet resistance values, film thickness, process uniformity and manufacturing equipment cleanliness, and other factors, integrated circuit passive electrical components often have tolerances that are approximately an order of magnitude worse than their analogous discrete external passive electrical components. Consequently, it has proven difficult and costly in the past to implement tuned networks or circuits using on-chip passive electrical components. One such tuned circuit is a voltage-controlled oscillator (VCO) in which a number of passive electrical devices are typically utilized to establish both the operating frequency and frequency offset of the VCO.
One well-known solution to this tolerance problem is to "trim" the integrated circuit until it operates within a set of pre-defined post-fabrication parameters. These "post-fabrication trimming" techniques are performed after manufacturing and testing the integrated circuit and are designed to physically alter the integrated circuit using a variety of methods including "Zener-zapping", laser trimming and fuse trimming. For example, using well-known fuse trimming techniques, fuseable links in an integrated circuit can be blown until the integrated circuit performs adequately under selected nominal conditions. Using these post-fabrication trimming techniques, passive electrical devices can be "fine-tuned" until they have acceptable tolerance values under nominal conditions. Disadvantageously, the trimming techniques produce only static solutions. For example, in fuse trimming, although the devices may perform adequately under nominal conditions, they may not perform adequately under all of the operating conditions of the integrated circuit. However, disadvantageously, the integrated circuit is permanently configured once the fuses are blown.
For example, as the voltage and temperature of the integrated circuit varies over time, offsets can be introduced despite the static settings created during the fuse trimming process. Devices that were once usable under the nominal conditions at which the fuses were blown may become unusable under some operating conditions, thus adversely affecting yield characteristics of the integrated circuits. In addition, the prior art post-fabrication solutions disadvantageously introduce additional manufacturing and testing steps into the manufacturing process. Using these prior art approaches, the manufacturer must first measure performance characteristics, trim the integrated circuits to conform to a selected set of performance and tolerance criteria, and test the results to ensure that the integrated circuit is trimmed appropriately. Thus, the prior art post-fabrication trimming techniques add additional time to the design and fabrication of integrated circuit devices and consequently add to the manufacturing costs of the integrated circuits.
Therefore, an improved method for improving the tolerances of passive electrical devices in an integrated circuit is needed which does not require the use of post-fabrication trimming techniques. Further, an improved method and apparatus is needed which dynamically monitors and corrects the performance characteristics of integrated circuits under all operating conditions. The improved method and apparatus should monitor and correct the performance characteristics of tuned networks especially as these performance characteristics are adversely affected by poor tolerances of on-chip passive electrical devices.
FIG. 1 shows a prior art attempt at solving the problem of implementing tuned circuits using on-chip passive electrical devices having poor or unacceptable tolerance values. As shown in FIG. 1, using an integrated switchable capacitor circuit 100, two terminals of an integrated tuned circuit (i.e., terminal A 101 and terminal B 103) can be selectively coupled to a bank of switchably connected capacitors (C.sub.1 through C.sub.n). Each of the capacitors is selectively coupled between the terminals 101, 103 by closing an associated and respective coupling switch S.sub.n. For example, capacitor C.sub.1 102 is coupled between the terminals 101, 103 by closing an associated switch S.sub.1 110. Similarly, capacitor C.sub.2 104 is coupled between the terminals 101, 103 by closing an associated switch S.sub.2 112. Finally, capacitor C.sub.n 108 is coupled between the terminals 101, 103 by closing an associated switch S.sub.n 116. Because the individual capacitors are connected in a parallel configuration, the total capacitance between the terminals 101, 103 is equal to the sum of the individual capacitors that are switched into the circuit (assuming that the switches do not also introduce capacitance to the circuit). By electrically connecting the terminals 101, 103 to a tuned circuit that is on the same integrated circuit as the switchable capacitor circuit 100, the capacitors can be selectively switched in and out of the tuned circuit, thereby changing the capacitance between the terminals 101, 103 to a desired value. Thus, despite the poor tolerance characteristics of the capacitors C.sub.1 through C.sub.n the tuned circuit can be adjusted to operate within desired parameters by simply changing the capacitance between terminals A 101 and B 103.
Disadvantageously, this prior art approach is undesirable when the tuned circuit operates at relatively high frequencies. For example, when the tuned circuit operates in the GHz range of operating frequencies, the bank of switches (e.g., 110, 112, 114, and 116) introduce significant loss into the tuned circuit and thereby degrade the circuit's performance characteristics. The prior art solution shown in FIG. 1 also disadvantageously increases both the amount of space (i.e., integrated circuit real estate) and the amount of power required to accommodate and operate the switches. Power requirements are increased due to the D.C. current required to operate the bank of switches.
Therefore, a need exists for a method and apparatus that can overcome the disadvantages associated with the prior art solutions and that will facilitate the integration of tuned capacitor networks on a single integrated circuit. The need exists for an apparatus that facilitates the fill integration of a calibrated tuned capacitor network such as a voltage-controlled oscillator (VCO). In addition, the need exists for an apparatus and method that can dynamically calibrate an integrated tuned capacitor network such as a VCO. The present invention provides such a method and apparatus. The present method and apparatus uses a one-bit or "binary" capacitor formed from a MOSFET transistor that can be switched from a first pre-determined capacitance value to a second pre-determined capacitance value by varying an applied control voltage between first and second pre-determined voltage values. A multi-bit digital capacitor can be implemented by connecting a bank of the binary capacitors in parallel, and by weighting the individual capacitors as desired. The multi-bit digital capacitor allows capacitance values to be customized to any desired and convenient value.